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This invention pertains to methods of manufacturing semiconductor devices. More particularly, the present invention is directed to a method of forming recesses and a damascene structure.
2. Description of the Related Art
Damascene processes form a metal interconnect network in forming multilevel metallization in semiconductor devices, such as integrated circuits. Damascene processes typically begin with a process step of forming a trench or a via in an insulating or dielectric layer on a semiconductor substrate. The trench or via is then filled with a suitable metal, usually copper, and excess metal is removed from the surface of the substrate by chemical mechanical polishing (CMP).
To provide electrical interconnection between two conductive features, such as a circuit line and a contact, which might be separated by an interposed insulating layer, a conductive via is formed through the insulating layer to electrically interconnect the two conductive features. Since a typical via is filled with a metal, such as copper, the via is referred to as a xe2x80x9cmetal contactxe2x80x9d or xe2x80x9cdamascenexe2x80x9d structure.
In forming a metal contact, a via, or a damascene structure, the top of the insulating layer is usually planarized before the metal is deposited. The insulating layer is typically formed of a dielectric material, such as silicon dioxide (SiO2). The dielectric layer is typically formed over a substrate, such as a silicon substrate. Because of the planarizing, the insulating layer can have a rough surface topography, with a rough surface topography. With a rough surface topography, the surface of the insulating layer typically is not entirely smooth and planar. It is difficult to conformally fill the insulating layer, which has a rough surface topography.
It is thus